DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 174

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Bus Controller
7.3.1
ABWCR designates each area as either an 8-bit access space or a 16-bit access space.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
7.3.2
ASTCR designates each area as either a 2-state access space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Rev. 6.00 Sep. 24, 2009 Page 126 of 928
REJ09B0099-0600
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
Bit Name
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Bus Width Control Register (ABWCR)
Access State Control Register (ASTCR)
Initial
Value
1
1
1
1
1
1
1
1
Initial
Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding area is to be
designated for 8-bit access or 16-bit access.
0: Area n is designated for 16-bit access
1: Area n is designated for 8-bit access
Note: n = 7 to 0
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding area is to be
designated as a 2-state access space or a 3-state access
space. Wait state insertion is enabled or disabled at the
same time.
0: Area n is designated for 2-state access
1: Area n is designated for 3-state access
Note: n = 7 to 0
Wait state insertion in area n external space is disabled
Wait state insertion in area n external space is enabled