DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 222

IC H8S/2552 MCU FLASH 176-LFBGA

DF2552BR26DV

Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Datasheets

Specifications of DF2552BR26DV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 Data Transfer Controller (DTC)
8.3
The DTC operates when activated by an interrupt request or by a write to DTVECR by software.
An activation interrupt request is specified by DTCER. When the corresponding bit is set to 1, it
becomes DTC activation source and when it is cleared to 0, it becomes CPU interrupt source. At
the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
interrupt flag of activation source or corresponding DTCER bit is cleared. Table 8.1 shows the
relationship between the activation source and DTCER clearing. The activation source flag, in the
case of RXI0, for example, is the RDRF flag in SCI_0.
Since there are a number of DTC activation sources, transferring the last byte (or word) does not
clear the flag of its activation source. Take appropriate steps at each interrupt processing.
When an interrupt has been designated as a DTC activation source, the existing CPU mask level
and interrupt controller priorities have no effect. If there are more than one activation sources at
the same time, the DTC operates in accordance with the default priority of the interrupt sources.
Figure 8.2 shows a block diagram of the DTC activation source control. For details, see section 5,
Interrupt Controller.
Rev. 6.00 Sep. 24, 2009 Page 174 of 928
REJ09B0099-0600
Bit
6
5
4
3
2
1
0
Bit Name
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
Activation Sources
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Software Activation Vector 6 to 0
These bits specify a vector number for the DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to DTVEC0 =
H'10, the vector address is H'0420.
These bits are writable when SWDTE = 0.

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