DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 760

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory
(a) Select the on-chip program to be downloaded
(b) Set the FEBS parameter necessary for erasure
(c) Erasure
(d) The return value in the erasing program, FPFR (general register R0L) is determined.
(e) Determine whether erasure of the necessary blocks has completed.
Rev. 6.00 Sep. 24, 2009 Page 712 of 928
REJ09B0099-0600
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is reported to the SS bit in the DPFR
parameter.
Specify the start address of a download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see Programming Procedure in User
Program Mode in section 20.4.2, (2), Programming Procedure in User Program Mode.
The procedures after setting parameters for erasing programs are as follows:
Set the erase block number of the user MAT in the flash erase block select parameter FEBS
(general register ER0). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
Similar to as in programming, there is an entry point of the erasing program in the area from
the start address of a download destination specified by FTDAR + 16 bytes of on-chip RAM.
The subroutine is called and erasing is executed by using the following steps.
MOV.L
JSR
NOP
•
•
•
If more than one block is to be erased, update the FEBS parameter and repeat steps (b) to (e).
Blocks that have already been erased can be erased again.
The general registers other than R0L are held in the erasing program.
R0L is a return value of the FPFR parameter.
Since the stack area is used in the erasing program, a stack area of maximum 128 bytes
must be allocated in RAM
#DLTOP+16,ER2
@ER2
; Set entry address to ER2
; Call erasing routine