DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 73

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.
2.1
• Upward-compatible with H8/300 and H8/300H CPU
• General-register architecture
• 65 basic instructions
• Eight addressing modes
• 16-Mbyte address space
• High-speed operation
⎯ Can execute H8/300 and H8/300H CPU object programs
⎯ Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
⎯ 8/16/32-bit arithmetic and logic instructions
⎯ Multiply and divide instructions
⎯ Powerful bit-manipulation instructions
⎯ Register direct [Rn]
⎯ Register indirect [@ERn]
⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
⎯ Immediate [#xx:8, #xx:16, or #xx:32]
⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)]
⎯ Memory indirect [@@aa:8]
⎯ Program: 16 Mbytes
⎯ Data:
⎯ All frequently-used instructions execute in one or two states
⎯ 8/16/32-bit register-register add/subtract
⎯ 8 × 8-bit register-register multiply
⎯ 16 ÷ 8-bit register-register divide
Features
16 Mbytes
Section 2 CPU
: 12 states
: 12 states
: 1 state
Rev. 6.00 Sep. 24, 2009 Page 25 of 928
REJ09B0099-0600
Section 2 CPU