DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 616

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
17.3.11 IEBus Reception Master Address Register 2 (IEMA2)
IEMA2 indicates the upper 8 bits of the communications destination master unit address in
slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the
contents are changed at the timing of setting the RxS flag in IERSR.
If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer
is not in the receive enabled state at control field reception, a receive error interrupt is generated
and the upper 8 bits of the master address are stored in IEMA2. This register cannot be modified
by a write.
17.3.12 IEBus Receive Control Field Register (IERCTL)
IERCTL indicates the control field value in slave/broadcast reception. This register is enabled
when slave/broadcast receive starts, and the contents are changed at the timing of setting the RxS
flag in IERSR.
This register cannot be modified.
Rev. 6.00 Sep. 24, 2009 Page 568 of 928
REJ09B0099-0600
Bit
7
6
5
4
3
2
1
0
Bit
7 to 4 ⎯
3
2
1
0
Bit Name
IMA11
IMA10
IMA9
IMA8
IMA7
IMA6
IMA5
IMA4
Bit Name
RCTL3
RCTL2
RCTL1
RCTL0
Initial Value
0
0
0
0
0
0
0
0
Initial Value
All 0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
Description
Upper 8 Bits of IEBus Reception Master Address
Indicates the upper 8 bits of the communications
destination master unit address in slave/broadcast
reception.
Description
Reserved
These bits are always read as 0.
IEBus Receive Control Field
Indicates the control field value in slave/broadcast
reception.