DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 652

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
17.6.3
1. The RxRDY flag indicates that IERBR stores data. Reading from IERBR by the DTC clears
2. If the CPU fails to read from IERBR by the timing of the frame reception or if the number of
3. The IEB receives data while the RxRDY flag is set and sets the OVE flag when the parity bit
4. On the transmit side, the unit continues retransfer until an ACK is received because it receives
5. If the OVE flag is cleared without loading the receive data from IERBR in the RxE interrupt
6. Item 5 above will not occur when the DTC transfer words is specified as the IERBFL value.
17.6.4
(1)
The AL Flag is set to 1 when arbitration is lost even if retransfer is performed for the number of
times specified by IEMCR after arbitration has been lost. The AL flag is not set when arbitration
is won during retransfer. If the AL flag is set to 1, the TxE flag is set and the wait state is entered.
(2)
If the UE flag is set to 1, the TxE flag is set and the wait state is entered. For details, see section
17.6.2, TxRDY Flag and Underrun Error.
(3)
If a timing error occurs during data transfer, the TTME and TxE flags are set, and the wait state is
entered.
Rev. 6.00 Sep. 24, 2009 Page 604 of 928
REJ09B0099-0600
the RxRDY flag. Meanwhile, the RxRDY flag must be cleared by software since reading from
IERBR by the CPU does not clear the RxRDY flag.
transfer words is less than the length specified by the message length bits, an overrun error
occurs.
reception starts. If the OVE flag is set when the acknowledge bit is transmitted, the IEB
assumes that an overrun error has occurred, returns a NAK, and discards the data in the receive
shift register.
a NAK.
handling routine caused when the OVE flag is set to 1, the IEB decides that the overrun error
has been cleared and sends an ACK to other units. In this case, the transmit unit completes the
communications correctly. However, no receive data is loaded from the IERBR and the receive
unit continues reception. Accordingly, in an interrupt handling routine caused by the OVE
flag, receive data must be loaded from IERBR, the RxRDY flag must be cleared. The DTC,
thus, should be ready to receive the next byte, and then the OVE flag must be cleared.
AL Flag
UE Flag
TTME Flag
RxRDY Flag and Overrun Error
Error Flag s in the IETEF