PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 251

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5.2
1.
2.
3.
4.
5.
6.
7.
 2010 Microchip Technology Inc.
Follow
Section 18.5.1 “Enable Host Mode and Dis-
cover a Connected Device” to discover a
device.
Set up the Endpoint Control register for
bidirectional control transfers by writing 0Dh to
U1EP0 (this sets the EPCONDIS, EPTXEN and
EPHSHK bits).
Place a copy of the device framework setup
command in a memory buffer. See “Chapter 9 of
the USB 2.0 Specification” for information on the
device framework command set.
Initialize the Buffer Descriptor (BD) for the
current (even or odd) TX EP0 to transfer the
eight bytes of command data for a device
framework command (i.e., GET
DESCRIPTOR):
a)
b)
Set the USB device address of the target device
in the address register (U1ADDR<6:0>). After a
USB bus Reset, the device USB address will be
zero. After enumeration, it will be set to another
value between 1 and 127.
Write D0h to U1TOK; this is a SETUP token to
Endpoint 0, the target device’s default control
pipe. This initiates a SETUP token on the bus,
followed by a data packet. The device hand-
shake is returned in the PID field of BD0STAT
after the packets are complete. When the USB
module updates BD0STAT, a transfer done
interrupt is asserted (the TRNIF flag is set). This
completes the setup phase of the setup transac-
tion as referenced in “Chapter 9 of the USB
Specification”.
To initiate the data phase of the setup transac-
tion (i.e., get the data for the GET
DESCRIPTOR command), set up a buffer in
memory to store the received data.
Set the BD data buffer address (BD0ADR)
to the starting address of the 8-byte
memory buffer containing the command.
Write 8008h to BD0STAT (this sets the
UOWN bit and sets a byte count of 8).
COMPLETE A CONTROL
TRANSACTION TO A CONNECTED
DEVICE
the
procedure
described
DEVICE
DEVICE
PIC24FJ256DA210 FAMILY
in
8.
9.
10. To initiate the status phase of the setup transac-
11. Initialize the current (even or odd) TX EP0 BD to
12. Write the Token register with the appropriate IN
Note:
Initialize the current (even or odd) RX or TX (RX
for IN, TX for OUT) EP0 BD to transfer the data.
a)
b)
Write the Token register with the appropriate IN
or OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 90h to U1TOK for
an IN token for a GET DEVICE DESCRIPTOR
command). This initiates an IN token on the bus
followed by a data packet from the device to the
host. When the data packet completes, the
BD0STAT is written and a transfer done interrupt
is asserted (the TRNIF flag is set). For control
transfers with a single packet data phase, this
completes the data phase of the setup transac-
tion as referenced in “Chapter 9 of the USB
Specification”. If more data needs to be
transferred, return to step 8.
tion, set up a buffer in memory to receive or send
the zero length status phase data packet.
transfer the status data:
a)
b)
or OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 01h to U1TOK for
an OUT token for a GET DEVICE DESCRIPTOR
command). This initiates an OUT token on the
bus followed by a zero length data packet from
the host to the device. When the data packet
completes, the BD is updated with the
handshake from the device and a transfer done
interrupt is asserted (the TRNIF flag is set). This
completes the status phase of the setup trans-
action as described in “Chapter 9 of the USB
Specification”.
Write C040h to BD0STAT. This sets the
UOWN, configures Data Toggle (DTS) to
DATA1 and sets the byte count to the length
of the data buffer (64 or 40h in this case).
Set BD0ADR to the starting address of the
data buffer.
Set the BDT buffer address field to the start
address of the data buffer.
Write 8000h to BD0STAT (set UOWN bit,
configure DTS to DATA0 and set byte count
to 0).
Only one control transaction can be
performed per frame.
DS39969B-page 251