PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 331

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 23-5:
REGISTER 23-6:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-3
bit 2
bit 1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
CSSL15
CSSL7
R/W-0
R/W-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
VBG6EN: A/D Input V
1 = Band gap voltage divided-by-six reference (V
0 = Band gap divided-by-six reference (V
VBG2EN: A/D Input V
1 = Band gap voltage divided-by-two reference (V
0 = Band gap divided-by-two reference (V
VBGEN: A/D Input V
1 = Band gap voltage reference (V
0 = Band gap reference (V
CSSL<15:0>: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan
CSSL14
CSSL6
R/W-0
R/W-0
U-0
U-0
—
—
ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER
AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
CSSL13
CSSL5
R/W-0
R/W-0
U-0
U-0
—
—
BG
BG
BG
Enable bit
/6 Enable bit
/2 Enable bit
BG
) is disabled
PIC24FJ256DA210 FAMILY
CSSL12
CSSL4
R/W-0
R/W-0
U-0
U-0
—
—
BG
) is enabled
BG
BG
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
/6) is disabled
/2) is disabled
CSSL11
CSSL3
R/W-0
R/W-0
U-0
U-0
—
—
BG
BG
/6) is enabled
/2) is enabled
VBG6EN
CSSL10
CSSL2
R/W-0
R/W-0
R/W-0
U-0
—
x = Bit is unknown
x = Bit is unknown
VBG2EN
CSSL9
CSSL1
R/W-0
R/W-0
R/W-0
U-0
—
DS39969B-page 331
VBGEN
CSSL8
CSSL0
R/W-0
R/W-0
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0