PIC24FJ256DA210T-I/BG Microchip Technology, PIC24FJ256DA210T-I/BG Datasheet - Page 310

• Manufacturer Part Number: PIC24FJ256DA210T-I/BG
• Description: 16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA210T-I/BG

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
REGISTER 22-5:
REGISTER 22-6:
DS39969B-page 310
bit 1
bit 0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPUBUSY
R-0, HSC
R-0, HSC
PUBUSY
PUBUSY: Processing Units are Busy Status bit
This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY or CHRBUSY.
1 = At least one processing unit is busy
0 = None of the processing units are busy
Unimplemented: Read as ‘0’
IPUBUSY: Inflate Processing Unit Busy Status bit
1 = IPU is busy
0 = IPU is not busy
RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit
1 = RCCGPU is busy
0 = RCCGPU is not busy
CHRBUSY: Character Graphics Processing Unit Busy Status bit
1 = CHRGPU is busy
0 = CHRGPU is not busy
VMRGN: Vertical Blanking Status bit
1 = Display interface is in the vertical blanking period
0 = Display interface is not in the vertical blanking period
HMRGN: Horizontal Blanking Status bit
1 = Display interface is in the horizontal blanking period
0 = Display interface is not in the horizontal blanking period
CMDLV: Command Watermark Level Status bit
The number of commands in the command FIFO changed from equal (=) to the command watermark
value to less than (<) the Command Watermark value set in CMDWMK (G1CON1<12:8>) register bits.
1 = Command in FIFO is less than the set CMDWMK value
0 = Command in FIFO is equal to or greater than the set CMDWMK value
CMDFUL: Command FIFO Full Status bit
1 = Command FIFO is full
0 = Command FIFO is not full
CMDMPT: Command FIFO Empty Status bit
1 = Command FIFO is empty
0 = Command FIFO is not empty
RCCBUSY
R-0, HSC
DPVSOE: Display Vertical Synchronization Port Enable bit
1 = V
0 = V
DPHSOE: Display Horizontal Synchronization Port Enable bit
1 = HSYNC port is enabled
0 = HSYNC port is disabled
U-0
—
G1CON3: DISPLAY CONTROL REGISTER 3 (CONTINUED)
SYNC
SYNC
G1STAT: GFX STATUS REGISTER
port is enabled
port is disabled
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
CHRBUSY
R-0, HSC
U-0
—
R-0, HSC
VMRGN
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0, HSC
HMRGN
U-0
—
R-0, HSC
CMDLV
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
R-0, HSC
CMDFUL
U-0
—
CMDMPT
R-0, HSC
U-0
—
bit 8
bit 0