16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R

PIC24FJ256DA210T-I/BG

Manufacturer Part NumberPIC24FJ256DA210T-I/BG
Description16-bit, 256KB Flash, 96K RAM, USB, Graphics 121 XBGA 10x10x1.20mm T/R
ManufacturerMicrochip Technology
SeriesPIC® 24F
PIC24FJ256DA210T-I/BG datasheets
 

Specifications of PIC24FJ256DA210T-I/BG

Core ProcessorPICCore Size16-Bit
Speed32MHzConnectivityI²C, IrDA, SPI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, GFX, LVD, POR, PWM, WDTNumber Of I /o84
Program Memory Size256KB (85.5K x 24)Program Memory TypeFLASH
Ram Size96K x 8Voltage - Supply (vcc/vdd)2.2 V ~ 3.6 V
Data ConvertersA/D 24x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case121-TFBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Page 323/408

Download datasheet (4Mb)Embed
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REGISTER 22-32: G1DBEN: DATA I/O PAD ENABLE REGISTER
R/W-0
R/W-0
R/W-0
GDBEN15
GDBEN14
GDBEN13
bit 15
R/W-0
R/W-0
R/W-0
GDBEN7
GDBEN6
GDBEN5
bit 7
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-0
GDBEN<15:0>: Display Data Pads Output Enable bits
1 = Corresponding display data (GD<x>) pin is enabled
0 = Corresponding display data (GD<x>) pin is disabled
GDBEN<15:0> can be used to disable or enable specific data signals while the DPPINOE bit
(G1CON3<9>) is set.
GDBENx
DPPINOE
(where x = 0 to 15)
1
1
0
 2010 Microchip Technology Inc.
PIC24FJ256DA210 FAMILY
R/W-0
R/W-0
GDBEN12
GDBEN11
R/W-0
R/W-0
GDBEN4
GDBEN3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Display data signal (GD) associated with GDBENx is enabled.
1
Display data signal (GD) associated with GDBENx is disabled.
0
Display data signal (GD) associated with GDBENx is disabled.
x
R/W-0
R/W-0
R/W-0
GDBEN10
GDBEN9
GDBEN8
bit 8
R/W-0
R/W-0
R/W-0
GDBEN2
GDBEN1
GDBEN0
bit 0
x = Bit is unknown
DS39969B-page 323