MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 17

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Asynchronous Bus Idle
Asynchronous Commands
Figure 9:
Asynchronous Addresses
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Asynchronous COMMAND LATCH Cycle
A target enters low-power standby when it is disabled and is not busy. If the target is busy
when it is disabled, the target enters standby after all of the LUNs complete their opera-
tions. Standby helps reduce power consumption.
A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
During bus idle, all of the signals are enabled except DQS, which is not used when the
asynchronous interface is active. No commands, addresses, and data are latched into the
target; no data is output.
An asynchronous command is written from I/O[7:0], DQ[7:0] to the command register
on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, andRE# is HIGH.
Commands are typically ignored by LUNs that are busy; however, some commands,
including READ STATUS (70h) and SELECT LUN WITH STATUS (78h), are accepted by
LUNs even when they are busy.
An asynchronous address is written from I/O[7:0], DQ[7:0] to the address register on the
rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Table 2 on page 23). The
number of cycles required for each command varies. Refer to the command descriptions
to determine addressing requirements (see “Command Definitions” on page 39").
Addresses are typically ignored by LUNs that are busy; however, some addresses are
accepted by LUNs even when they are busy; for example, like address cycles that follow
the SELECT LUN WITH STATUS (78h) command.
I/Ox, DQx
WE#
ALE
CE#
CLE
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
17
t WP
t CS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMMAND
t CLS
t ALS
t DS
t CLH
t CH
t ALH
t DH
©2008 Micron Technology, Inc. All rights reserved.
Bus Operation
Don’t Care
Advance