MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 56

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Status Operations
Table 14:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
SR
Bit
7
6
5
4
3
2
Definition
ARDY
WP#
RDY
Status Register Definition
–
–
–
Independent
per Plane
Each LUN provides its status independently of other LUNs on the same target through
its 8-bit status register.
After the READ STATUS (70h) or SELECT LUN WITH STATUS (78h) command is issued,
status register output is enabled. The contents of the status register are returned on
I/O[7:0], DQ[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled, changes
in the status register are seen on I/O[7:0], DQ[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
When the synchronous interface is active and status register output is enabled, changes
in the status register are seen on I/O[7:0], DQ[7:0] as long as CE# and W/R# are LOW and
ALE and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (
command to disable the status register and enable data output (see READ MODE 00h on
page 55).
The READ STATUS (70h) command returns the status of the most recently selected LUN.
To prevent data contention during or following a multi-LUN operation, the host must
enable only one LUN for status output by using the SELECT LUN WITH STATUS (78h)
command (see “Multi-LUN Operations” on page 86).
–
–
–
–
–
–
1
Write Protect:
"0" = Protected
"1" = Not protected
In the normal array mode, this bit indicates the value of the WP# signal. In OTP
mode this bit is set to "0" if a PROGRAM OTP PAGE operation is attempted and
the OTP area is protected.
Ready/Busy I/O:
"0" = Busy
"1" = Ready
This bit indicates that the selected LUN is not available to accept new commands,
address, or data I/O cycles with the exception of RESET (FFh), SYNCHRONOUS
RESET (FCh), READ STATUS (70h), and SELECT LUN WITH STATUS (78h). This bit
applies only to the selected LUN.
Ready/Busy Array:
"0" = Busy
"1" = Ready
This bit goes LOW (busy) when an array operation is occurring on any plane of the
selected LUN. It goes HIGH when all array operations on the selected LUN finish.
This bit applies only to the selected LUN.
Reserved (0)
Reserved (0)
Reserved (0)
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
t
R) is complete, the host must issue the READ MODE (00h)
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
Command Definitions
©2008 Micron Technology, Inc. All rights reserved.
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