MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 70

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Figure 45:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Cycle type
(DQ[7:0])
I/O[7:0]
RDY
READ PAGE MULTI-PLANE (00h–32h) Operation
Command
00h
Note:
Note:
Note:
Address
C1
3. 32h is written to the command register. (The column address in the address specified
1. R/B# goes LOW and the LUN is busy (RDY = 0, ARDY = 0) for
2. R/B# goes HIGH and the LUN is ready (RDY = 1, ARDY = 1).
3. The LUN and block are queued for data transfer from the array to the cache register
4. The READ PAGE (00h-30h) command is issued.
5. Data is transferred from the NAND Flash array for all of the addressed planes to their
6. When the LUN is ready (RDY = 1, ARDY = 1), data output is enabled for the cache reg-
7. When the host requests data output, it begins at the column address specified in the
After this command is issued, the following sequence occurs:
See “Multi-Plane Addressing” on page 86 for additional multi-plane addressing require-
ments.
is ignored.)
During
commands (FFh, FCh). Following
the only valid commands are status operations (70h, 78h), READ PAGE MULTI-PLANE
(00h-32h), and READ PAGE (00h-30h).
for the addressed plane.
Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue
additional planes for data transfer.
respective cache registers.
ister linked to the even plane.
READ PAGE (00h-30h) command.
To enable data output in the other cache registers, the SELECT CACHE REGISTER
(06h-E0h) command can be issued. Also, to change the column address within the
currently selected plane, the CHANGE READ COLUMN (05h-E0h) command can be
issued.
Address
C2
t
DBSY, the only valid commands are status operations (70h, 78h) and reset
Micron Confidential and Proprietary
Address
R1
8Gb Asychronous/Synchronous NAND Flash Memory
Address
R2
70
Address
R3
t
DBSY, to continue the multi-plane read operation,
Command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32h
t WB
t DBSY
Command
Command Definitions
00h
©2008 Micron Technology, Inc. All rights reserved.
t
DBSY.
Address
C1
Address
...
Advance