MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 41

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Reset Operations
RESET (FFh)
Figure 28:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
I/Ox (DQx)
WE#
R/B#
CE#
CLE
Asynchronous RESET (FFh) Cycle
command
RESET
The RESET (FFh) command is used to put a target into a known condition and to abort
command sequences in progress. This command is accepted by all LUNs, even when
they are busy.
When FFh is written to the command register, the target goes busy for
the selected target (CE#) discontinues all array operations on all LUNs. All pending
single-plane and multi-plane operations are cancelled. If this command is issued while a
PROGRAM or ERASE operation is occurring on one or more LUNs, the data may be
partially programmed or erased and is invalid. The command register is cleared and
ready for the next command. The data register and cache register contents are invalid.
If the RESET (FFh) command is issued when the synchronous interface is enabled, the
target's interface is changed to the asynchronous interface and the timing mode is set to
“0”. The RESET (FFh) command can be issued asynchronously when the synchronous
interface is active, meaning that CLK does not need to be continuously running when
CE# is transitioned LOW and FFh is latched on the rising edge of CLK. After this
command is latched, the host should not issue any commands during
and during or after
If the RESET (FFh) command is issued when the asynchronous interface is active, the
target's asynchronous timing mode remains unchanged. During or after
can poll each LUN's status register.
RESET must be issued as the first command to each target following power-up (see “Vcc
Power Cycling” on page 35). Use of the SELECT LUN WITH STATUS (78h) command is
prohibited during the power-on RESET. To determine when the target is ready, use READ
STATUS (70h).
FFh
t WB
Micron Confidential and Proprietary
t
8Gb Asychronous/Synchronous NAND Flash Memory
RST, the host can poll each LUN's status register.
t RST
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command Definitions
©2008 Micron Technology, Inc. All rights reserved.
t
RST. During
t
ITC. After
t
RST, the host
Advance
t
ITC,
t
RST,