MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 67

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

READ PAGE CACHE LAST (3Fh)
Figure 44:
PAGE READ MULTI-PLANE (00h-32h) using Cache
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Cycle type
(DQ[7:0])
I/O[7:0]
RDY
(SEQUENTIAL OR RANDOM)
READ PAGE CACHE
Page Address N
As defined for
Command
READ PAGE CACHE LAST (3Fh) Operation
31h
t WB
t RCBSY
1. R/B# goes LOW and the LUN is busy (RDY = 0, ARDY = 0) for
2. R/B# goes HIGH and the LUN is ready (RDY = 1, ARDY = 1).
3. Data can be output from the cache register beginning at column address 0. The
1. The SELECT LUN WITH STATUS (78h) command is issued.
2. The READ MODE (00h) command is issued.
1. 00h is written to the command register.
2. Five address cycles are written to the address register.
3. 32h is written to the command register. (The column address in the address specified
1. R/B# goes LOW and the LUN is busy (RDY = 0, ARDY = 0) for
The READ PAGE CACHE LAST (3Fh) command ends the READ PAGE CACHE sequence
and copies a page from the data register to the cache register. This command is accepted
by the LUN when it is ready (RDY = 1, ARDY = 1). It is also accepted by the LUN during
READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1, ARDY = 0).
This command is issued when 3Fh is written to the command register. After the
command is issued, the following sequence occurs:
In devices that have more than one LUN per target, during and following multi-LUN
operations, this sequence is followed to select only one LUN and prevent bus conten-
tion:
The READ PAGE MULTI-PLANE (00h-32h) can be used to setup multi-plane cache read
operations. The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to
transfer data from the NAND flash array to its cache register. This command can be
issued one or more times. Each time a new plane address is specified, that pane is also
queued for data transfer. The command is issued to select the final plane and to begin
the read operation for all previously queued planes.
This command is issued in the following sequence:
After this command is issued, the following sequence occurs:
CHANGE READ COLUMN (05h-E0h) command can be used to change the column
address of the data being output from the cache register.
is ignored.)
RR
D
D0
OUT
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
D
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OUT
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Dn
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Command
3Fh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WB
t RCBSY
t RR
Command Definitions
D
D0
©2008 Micron Technology, Inc. All rights reserved.
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t
t
RCBSY.
DBSY.
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