MT29F8G08ABABAWP-IT:B Micron Technology Inc, MT29F8G08ABABAWP-IT:B Datasheet - Page 21

• Manufacturer Part Number: MT29F8G08ABABAWP-IT:B
• Description: MICMT29F8G08ABABAWP-IT:B 8GB ASYNCHRONOU
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP-IT:B

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 30b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1G
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

Write Protect (WP#)
Ready/Busy# (R/B#)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Where Σ
Where R
The WP# signal enables or disables PROGRAM and ERASE operations to a target. When
WP# is LOW, PROGRAM and ERASE operations are disabled. When WP# is HIGH,
PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until Vcc and VccQ
are stable to prevent inadvertent PROGRAM and ERASE operations (see “Vcc Power
Cycling” on page 35 for additional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned the host must wait
issuing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should not
be multiplexed with other signals.
The R/B# signal provides a hardware method of indicating whether a target is ready or
busy. A target is busy when one or more of its LUNs are busy (RDY = "0"). A target is ready
when all of its LUNs are ready (RDY = "1"). Because each LUN contains a status register,
it is possible to determine the independent status of each LUN by polling its status
register instead of using the R/B# signal (see “Status Operations” on page 56 for details
regarding LUN status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller (see Figure 14 on page 22).
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing
requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10-
to 90-percent points on the R/B# waveform, the rise time is approximately two time
constants (TC).
The fall time of the R/B# signal is determined mainly by the output impedance of the R/
B# signal and the total load capacitance. Approximate Rp values using a circuit load of
100pF are provided in Figure 19 on page 24.
The minimum value for Rp is determined by the output drive capability of the R/B#
signal, the output voltage swing, and VCCQ.
IL
=
is the sum of the input currents of all devices tied to the R/B# pin.
Rp (resistance of pull-up resistor), and C
Micron Confidential and Proprietary
Rp
8Gb Asychronous/Synchronous NAND Flash Memory
=
V
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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total capacitive load.
©2008 Micron Technology, Inc. All rights reserved.
Bus Operation
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