PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 102

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Figure 19: Clock Slave: H-MVIP
When Clock Slave: H-MVIP mode is enabled a 8.192Mb/s H-MVIP egress
interface multiplexes up to 672 channels from 28 T1s or 21 E1s, up to 672
channel associated signaling (CAS) channels from 28 T1s or 21 E1s and
common channel signaling from up to 28 T1s or 21 E1s. The H-MVIP interfaces
use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for
synchronization.
Seven H-MVIP data signals, MVED[1:7], share pins with serial PCM data inputs,
ED[x], to provide H-MVIP access for up to 672 data channels. The H-MVIP
mapping is fixed such that each group of four nearest neighbor T1 or E1 links
make up the individual 8.192Mb/s H-MVIP signal. The multiplexed data input is
shared with the lowest numbered T1 or E1 serial PCM link in the bundle, for
example MVED[2] combines the DS0s or timeslots of ED[5,6,7,8] and is pin
multiplexed with ED[5]. This mode is selected when the SYSOPT[2:0] bits in the
Global Configuration register are set to H-MVIP.
A separate seven signal H-MVIP interface is for access to the channel
associated signaling for 672 channels. The CAS H-MVIP interface is time
division multiplexed exactly the same way as the data channels. The CAS H-
MVIP is synchronized with the H-MVIP data channels when SYSOPT[2:0] is set
to H-MVIP mode. Over a T1 or E1 multi-frame the four CAS bits per channel are
repeated with each data byte. Four stuff bits are used to pad each CAS nibble
(ABCD bits) out to a full byte in parallel with each data byte. The egress CAS H-
MVIP interface, CASED[1:7], is multiplexed with seven serial PCM egress data
pins, ED[2,6,10,14,18,22,26].
The CAS H-MVIP interface can be used in parallel with the SBI Add bus as an
alternative method for accessing the CAS bits while data transfer occurs over the
SBI bus. This is selected when the SYSOPT[2:0] bits in the Global Configuration
register are set to “SBI Interface with CAS or CCS H-MVIP Interface” and the
ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set to 0.
Inputs Tim ed
to CMV8MC LK
C MV8MCLK
CASED[1:7]
MVED [1:7]
C MVFPC
CMVFP
CC SED
Inte rface
System
Egress
ESIF
ISSUE 1
T1-XB AS/E1-TRAN
Frame Gene ration,
Signaling Insertion,
Trunk Co nditioning
BasicTransm itter:
Alarm Insertion,
Line Coding
89
Digital PLL
TJAT
TJAT
FIFO
TRANSMITTER
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3
Transmit C LK[1:28]
Transmit D ata[1:28]