PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 218

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
(CSB+WRB)
Figure 80: Microprocessor Interface Write Timing
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB
2. In non-multiplexed address/data bus architectures, ALE should be held high
3. Parameter tHAW is not applicable if address latching is used.
4. When a set-up time is specified between an input and a clock, the set-up
5. When a hold time is specified between an input and a clock, the hold time is
signals.
so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable.
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
D[7:0]
A[9:0]
ALE
ISSUE 1
tS
ALW
tV
tS
L
AW
tS
Valid Address
LW
205
tS
tV
Valid Data
WR
DW
tH
ALW
tH
tH
DW
tH
LW
AW
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3