PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 177

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24 signaling
bits.
Table 18: T1 Channel Associated Signaling bits
Note that in synchronous mode, the SF/ESF F-bits may have arbitrary alignment
with respect to the P
T1 level. However, CAS is always aligned to the P
synchronous or asynchronous mode).
T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary
link rate adjustments are optionally passed across the SBI via the V4. T1
tributary alarm conditions are optionally passed across the SBI bus via the link
rate octet in the V4 location.
In synchronous mode the T1 tributary mapping is fixed to that shown in Table 17
and rate justifications are not possible using the V3 octet. The clock rate
A13
A17
A21
B13
B17
B21
C13
C17
C21
D13
D17
D21
A1
A5
A9
B1
B5
B9
C1
C5
C9
D1
D5
D9
S
1
A10
A14
A18
A22
B10
B14
B18
B22
C10
C14
C18
C22
D10
D14
D18
D22
A2
A6
B2
B6
C2
C6
D2
D6
S
2
A15
A19
A23
B15
B19
B23
C11
C15
C19
C23
D11
D15
D19
D23
A11
B11
A3
A7
B3
B7
C3
C7
D3
D7
S
3
1
ISSUE 1
P
0
phase alignment bits, due to possible frame slips at the
A12
A16
A20
A24
B12
B16
B20
B24
C12
C16
C20
C24
D12
D16
D20
D24
A4
A8
B4
B8
C4
C8
D4
D8
S
4
SF
F1
S1
F2
S2
F3
S3
F4
S4
F5
S5
F6
S6
F1
S1
F2
S2
F3
S3
F4
S4
F5
S5
F6
S6
F
ESF
M10
M11
M12
M2
M3
M5
M6
M1
C1
C2
M4
C3
M7
C4
M8
M9
C5
C6
164
F1
F2
F3
F4
F5
F6
F
P
1
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
11
11
11
11
11
11
P
0
1
P
0
bits (i.e. in either
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3