PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 196

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
13
13.1 DS3 Line Side Interface Timing
PROPRIETARY AND CONFIDENTIAL
FUNCTIONAL TIMING
All functional timing diagrams assume that polarity control is not being applied to
input and output data and clock lines (i.e. polarity control bits in the TECT3
registers are set to their default states).
Figure 48: Receive Bipolar DS3 Stream
The Receive Bipolar DS3 Stream diagram (Figure 48) shows the operation of the
TECT3 while processing a B3ZS encoded DS3 stream on inputs RPOS and
RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated
corresponds to a valid B3ZS signature. A line code violation is declared upon
detection of three consecutive zeros in the incoming stream, or upon detection of
a bipolar violation which is not part of a valid B3ZS signature.
Figure 49: Receive Unipolar DS3 Stream
The Receive Unipolar DS3 Stream diagram (Figure 49) shows the complete DS3
receive signal on the RDAT input. Line code violation indications, detected by an
upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each
bit period. The PMON Line Code Violation Event Counter is incremented each
time a logic 1 is sampled on RLCV.
RNEG
RPOS
RCLK
RDAT
RCLK
RLCV
X1 BIT
INFO 1
ISSUE 1
INFO 84
X2 BIT
OR P OR M BIT
183
INFO 84
3 consec 0s
C BIT
OR F BIT
INFO 1
LCV
INFO 2
HIGH DENSITY T1/E1 FRAMER
INFO 3
LCV INDICATION
AND M13 MULTIPLEXER
PM4328 TECT3
INFO 4
INFO 5