PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 148

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
F x : M-Subframe Alignment Signal
C x : C-Bit Channels
· Transmit: The TECT3 generates the M-Subframe Alignment signal (F1=1,
· Receive: The TECT3 finds M-frame alignment by searching for the F-bits
· Transmit: When configured for M23 applications, the C-bits are forced to
· Receive: The CBITV register bit in the DS3 FRMR Status register is used
registers. When one or more M-bit errors are detected in 3 out of 4
consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the
DS3 Framer Configuration register is a logic 0).
F2=0, F3=0, F4=1).
and the M-bits. Out-of-frame is removed if the M-bits are correct for three
consecutive M-frames while no discrepancies have occurred in the F-bits.
F-bit errors are counted in the DS3 PMON Framing Bit Error Event Count
registers. An out-of frame defect is asserted if 3 F-bit errors out of 8 or 16
consecutive F-bits are observed (as selected by the M3O8 bit in the DS3
FRMR Configuration register).
logic 1 with the exception of the C-bit Parity ID bit (the first C-bit of the first
M-subframe), which is forced to toggle every M-frame.
When configured for C-bit parity applications, the C-bit Parity ID bit is
forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The
third C-bit in M-subframe 1 provides a far-end alarm and control (FEAC)
signal. The FEAC channel is sourced by the DS3 XBOC block. The 3 C-
bits in M-subframe 3 carry path parity information. The value of these 3 C-
bits is the same as that of the P-bits. The 3 C-bits in M-subframe 4 are the
FEBE bits. FEBE transmission is controlled by the DFEBE bit in the DS3
TRAN Diagnostic register and by the detection of receive framing bit and
path parity errors. The 3 C-bits in M-subframe 5 contain the 28.2 kbit/s
path maintenance datalink. These bits are inserted from the DS3 TDPR
HDLC controller. The C-bits in M-subframes 2, 6, and 7 are unused and
are set to logic 1.
to report the state of the C-bit parity ID bit, and hence whether a M23 or C-
bit parity DS3 signal stream is being received. The FEAC channel on the
third C-bit in M-subframe 1 is detected by the DS3 RBOC block. Path
parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are
reported in the DS3 PMON Path Parity Error Event Count and FEBE Event
Count registers respectively. The path maintenance datalink signal is
extracted by theDS3 RDLC HDLC receiver (if enabled).
ISSUE 1
135
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3