PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 52

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
Pin Name
MVID[1]
MVID[2]
MVID[3]
MVID[4]
MVID[5]
MVID[6]
MVID[7]
CASID[1]
CASID[2]
CASID[3]
CASID[4]
CASID[5]
CASID[6]
CASID[7]
PROPRIETARY AND CONFIDENTIAL
Type
Output AA5
Output Y6
ISSUE 1
Pin
No.
R19
Y2
P21
U2
M19
J1
P20
W2
P22
V4
L19
H4
Function
SYSOPT[2:0] bits in the Global Configuration register.
The CMVFPB frame pulse occurs every 125us for a
and is sampled on the falling edge of CMVFPC.
This signal shares a pin with CEFP. By default this
input is CEFP.
H-MVIP Ingress Data (MVID[1:7]). MVID[x] carries the
recovered T1 or E1 channels which have passed
through the elastic store. Each MVID[x] signal carries
the channels of four complete T1s or E1s. MVID[x]
carries the T1 or E1 data equivalent to ID[(4x-3):(4x)].
MVID[x] is aligned to the common H-MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. MVID[x] is updated on every
second rising or falling edge of the common H-MVIP
16.384Mb /s clock, CMV8MCLK, as fixed by the
common H-MVIP frame pulse clock, CMVFPC. The
updating edge of CMV8MCLK is selected via the
CMVIDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
In E1 mode only MVID[1:6] are used.
MVID[1:7] shares the same pins as
ID[1,5,9,13,17,21,25].
Channel Associated Signaling Ingress Data
(CASID[1:7]). CASID[x] carries the channel associated
signaling stream extracted from all the T1 or E1
channels. Each CASID[x] signal carries CAS for four
complete T1s or E1s. CASID[x] carries the
corresponding CAS values of the channel carried in
MVID[x].
CASID[x] is aligned to the common H-MVIP
16.384Mb/s clock, CMV8MCLK, frame pulse clock,
CMVFPC, and frame pulse, CMVFPB. CASID[x] is
updated on every second rising or falling edge of
CMV8MCLK as fixed by the common H-MVIP frame
pulse clock, CMVFPC. The updating edge of
CMV8MCLK is selected via the CMVIDE bit in the
Master Common Ingress Serial and H-MVIP Interface
39
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3