PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 51

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
Pin Name
H-MVIP System Side Interfaces
CMV8MCLK
CMVFPC
CMVFPB
PROPRIETARY AND CONFIDENTIAL
Type
Input
Input
Input
ISSUE 1
Pin
No.
N4
N1
M2
Function
Common 8M H-MVIP Clock (CMV8MCLK). The
common 8.192 Mbps H-MVIP data provides the data
clock for receive and transmit links configured for
operation in 8.192 Mbps H-MVIP mode.
CMV8MCLK is used to sample data on MVID[1:7],
MVED[1:7], CASID[1:7], CASED[1:7], CCSID and
CCSED. CMV8MCLK is nominally a 50% duty cycle
clock with a frequency of 16.384MHz.
The H-MVIP interfaces are enabled via the
SYSOPT[2:0] bits in the Global Configuration register.
This signal shares a pin with CECLK. By default this
input is CECLK.
Common H-MVIP Frame Pulse Clock (CMVFPC).
The common 8.192 Mbps H-MVIP frame pulse clock
provides the frame pulse clock for receive and transmit
links configured for operation in 8.192 Mbps H-MVIP
mode.
CMVFPC is used to sample CMVFPB. CMVFPC is
nominally a 50% duty cycle clock with a frequency of
4.096 MHz. The falling edge of CMVFPC must be
aligned with the falling edge of CMV8MCLK with no
more than ±10ns skew.
The H-MVIP interfaces are enabled via the
SYSOPT[2:0] bits in the Global Configuration register.
This signal shares a pin with CICLK. By default this
input is CICLK.
Common H-MVIP Frame Pulse (CMVFPB). The
active low common frame pulse for 8.192 Mbps H-
MVIP signals references the beginning of each frame
for links operating in 8.192Mbps H-MVIP mode.
The H-MVIP interfaces are enabled via the
ECLK[1]/EFP[1]/ESIG[1] shares a pin with the
DS3 system interface output signal
TFPO/TMFPO/TGAPCLK.
38
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3