PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 199
PM4328-PI
Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM4328-PI.pdf
(250 pages)
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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
Figure 54: Framer Mode DS3 Receive Output Stream
Figure 55: Framer Mode DS3 Receive Output Stream with RGAPCLK
The DS3 Framer Only Mode Receive Output Stream diagram (Figure 54) shows
the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the
OPMODE[1:0] bits are set to “DS3 Framer Only mode” in the Global
Configuration register. Figure 54 shows the data streams when the TECT3 is
configured for the DS3 receive format. If the RXMFPO bit in the DS3 Master
Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse
high for one RSCLK cycle on first bit of each M-subframe with alignment to the
RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure
54), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output
stream. ROVRHD will be high for every overhead bit position on the RDATO
data stream. Figure 55 shows the output data stream with RGAPCLK in place of
RSCLK when the RXGAPEN bit in the DS3 Master Unchannelized Interface
Options register set to logic 1. RGAPCLK remains high during the overhead bit
positions.
RFPO/RMFPO
RGAPCLK
ROVRHD
RDATO
RDATO
RSCLK
INFO
82
INFO
82
INFO
83
INFO
83
INFO
84
INFO
84
ISSUE 1
F
4
INFO
82
INFO
82
INFO
83
INFO
83
INFO
84
INFO
84
186
X
1
INFO
1
INFO
1
INFO
2
INFO
2
X
2
INFO
1
INFO
1
INFO
2
INFO
2
INFO
3
INFO
3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
INFO
82
INFO
82
PM4328 TECT3
INFO
83
INFO
83
INFO
84
INFO
84
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