PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 200

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PM4328-PI

Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet

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DATASHEET
PMC-2011596
13.3 SBI DROP Bus Interface Timing
PROPRIETARY AND CONFIDENTIAL
Figure 56: SBI DROP Bus T1 Functional Timing
Figure 56 illustrates the operation of the SBI DROP Bus, using a negative
justification on the second to last V3 octet as an example. The justification is
indicated by asserting SDPL high during the V3 octet. The timing diagram also
shows the location of one of the tributaries by asserting SDV5 high during the V5
octet. The SBIACT signal is shown for the case in which TECT3 is driving
SPE#1 onto the SBI DROP bus.
Figure 57: SBI DROP Bus DS3 Functional Timing
SDDATA[7:0
Figure 57 shows three DS-3 tributaries mapped onto the SBI bus. A negative
justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A
positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3
which has SDPL asserted low. The SBIACT signal is shown for the case in
which TECT3 is driving SPE#2 (DS-3#2) onto the SBI DROP bus.
SDDATA[7:0]
SREFCLK
SREFCLK
SBIACT
SC1FP
SDDP
SDV5
SBIACT
SDPL
SC1FP
SDDP
SDPL
SDV5
]
C1
C1
ISSUE 1
···
···
···
···
···
···
···
187
H3
···
···
···
···
···
···
···
H3
V3
H3
V3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
V3 DS0#4. V5 DS0#9.
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3

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