PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 208

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
13.8 Ingress Serial Clock and Data Interface Timing
PROPRIETARY AND CONFIDENTIAL
ICLK[x]
IFP[x]
ID[x]
ICLK[x]
IFP[x]
ID[x]
The Egress Interface is configured for the Clock Slave: Clear Channel mode by
writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register.
ED[x] is clocked in on the rising edge of the ECLK[x] input. When the EDE bit in
the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is
sampled on the falling edge of ECLK[x], and the functional timing is described by
Figure 70 with the ECLK[x] signal inverted.
Figure 71: T1 Ingress Interface Clock Master : Full Channel Mode
Figure 72: E1 Ingress Interface Clock Master : Full Channel Mode
The IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register
are programmed to select the Clock Master: Full Channel mode. IFP[x] is set
high for one ICLK[x] period every frame. When the IMFP bit in the T1/E1 Serial
Interface Configuration register are set to 1, IFP[x] pulses on the superframe
frame boundaries (i.e. once every 12 or 24 frame periods when configured for T1
operation or once every CRC or signaling multiframe when configured for E1
operation). The IMFPCFG[1:0] bits select whether IFP[x] indicates E1 CRC,
signaling or both CRC and signaling multiframe boundaries. If ALTIFP=1, IFP[x]
pulses on every second frame or the multiframe boundary.
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Channel 24
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Timeslot 31
F-bit or Parity
(if enabled)
Parity Bit
Channel 1
ISSUE 1
Timeslot 0
Channel 2
Timeslot 1
195
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8
Channel 24
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Timeslot 31
F-bit or Parity
HIGH DENSITY T1/E1 FRAMER
(if enabled)
Parity Bit
AND M13 MULTIPLEXER
Channel 1
PM4328 TECT3
Timeslot 0
1