PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 202
PM4328-PI
Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM4328-PI.pdf
(250 pages)
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STANDARD PRODUCT
DATASHEET
PMC-2011596
13.6 Ingress H-MVIP Link Timing
PROPRIETARY AND CONFIDENTIAL
CMV8MCLK
CMV8MCLK
(16 MHz)
Figure 59: Egress 8.192 Mbps H-MVIP Link Timing
The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame
pulse clock, CMVFPC, data, MVID[x], CASID[x] or CCSID, and frame pulse,
CMVFPB, signals of a link configured for 8.192 Mbps H-MVIP operation with a
type 0 frame pulse is shown in Figure 60. The falling edges of each CMVFPC
are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbps H-
MVIP operation. The TECT3 samples CMVFPB low on the falling edge of
CMVFPC and references this point as the start of the next frame. The TECT3
updates the data provided on MVID[x], CASID[x] and CCSID on every second
falling edge of CMV8MCLK as indicated for bit 2 (B2) of time-slot 1 (TS 1) in
Figure 60. The first bit of the next frame is updated on MVID[x], CASID[x] and
CCSID on the falling CMV8MCLK clock edge for which CMVFPB is also sampled
low. B1 is the most significant bit and B8 is the least significant bit of each octet.
Figure 60: Ingress 8.192 Mbps H-MVIP Link Timing
(16 MHz)
(4 MHz)
(4 MHz)
CASED[x]
CMVFPC
CMVFPC
CMVFPB
CMVFPB
MVED[x]
CASID[x]
CCSED
MVID[x]
CCSID
TS 127
TS 127
B8
B8
B1
B1
ISSUE 1
B2
B2
B3
B3
189
B4
B4
TS 0
TS 0
B5
B5
B6
B6
B7
B7
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
B8
B8
PM4328 TECT3
B1
B1
TS 1
TS 1
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