PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 82

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
9.15 Bit Oriented Code Generator (XBOC)
9.16 HDLC Transmitters (TDPR)
PROPRIETARY AND CONFIDENTIAL
bits for the current superframe before switching to the new values. This permits
signaling integrity to be preserved independent of the superframe alignment of
the T1-XBAS or the signaling data source.
The Bit Oriented Code Generator function is provided by the XBOC block. This
block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link
(FDL) channel in ESF framing format, as defined in ANSI T1.403-1989 or in the
DS3 C-bit parity Far-End Alarm and Control (FEAC) channel. The 64 th code
(111111) is similar to the HDLC Flag sequence and is used in the XBOC to
disable transmission of any bit oriented codes. When transmission is disabled
the FDL or FEAC channel is set to all ones.
Bit oriented codes are transmitted on the T1 Facility Data Link or DS3 Far-End
Alarm and Control channel as a 16-bit sequence consisting of 8 ones, a zero, 6
code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as
the code is not 111111. When driving the T1 facility data link the transmitted bit
oriented codes have priority over any data transmitted except for ESF Yellow
Alarm. The code to be transmitted is programmed by writing to the XBOC code
registers when it is held until the last code has been transmitted at least 10
times. An interrupt or polling mechanism is used to determine when the most
recent code written the XBOC register is being transmitted and a new code can
be accepted.
The HDLC Transmitter (TDPR) provides a serial data link for the 4 kHz ESF
facility data link, E1 Sa-bit data link, the DS3 C-bit parity path maintenance data
link or a specified channel within a T1 or E1 stream. The TDPR is used under
microprocessor control to transmit HDLC data frames. It performs all of the data
serialization, CRC generation, zero-bit stuffing, as well as flag, and abort
sequence insertion. Upon completion of the message, a CRC-CCITT frame
check sequence (FCS) may be appended, followed by flags. If the TDPR
transmit data FIFO underflows, an abort sequence is automatically transmitted.
When enabled, the TDPR continuously transmits the flag sequence (01111110)
until data is ready to be transmitted. Data bytes to be transmitted are written into
the Transmit Data Register. The TDPR performs a parallel-to-serial conversion
of each data byte before transmitting it.
The default procedure provides automatic transmission of data once a complete
packet is written. All complete packets of data will be transmitted. After the last
data byte of a packet, the CRC word (if CRC insertion has been enabled) and a
ISSUE 1
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HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PM4328 TECT3