HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 126

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Interrupt Controller (INTC)
6.3.1
ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input
pins NMI and IRQ0 to IRQ7 and indicates the input signal level at the NMI pin.
Bit
15
14 to 9
8
7
6
5
Rev.4.00 Mar. 27, 2008 Page 80 of 882
REJ09B0108-0400
Bit Name Initial Value
NMIL
—
NMIE
IRQ0S
IRQ1S
IRQ2S
Interrupt Control Register 1 (ICR1)
All 0
0
1/0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
Description
NMI Input Level
Sets the level of the signal input to the NMI pin. This
bit can be read to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
Reserved
These bits are always read as 0. The write value
should always be 0.
NMI Edge Select
0: Interrupt request is detected on falling edge of NMI
1: Interrupt request is detected on rising edge of NMI
IRQ0 Sense Select
This bit sets the IRQ0 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ0
1: Interrupt request is detected on edge of IRQ0 input
IRQ1 Sense Select
This bit sets the IRQ1 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ1
1: Interrupt request is detected on edge of IRQ1 input
IRQ2 Sense Select
This bit sets the IRQ2 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ2
1: Interrupt request is detected on edge of IRQ2 input
input
input
input
(edge direction is selected by ICR2)
input
(edge direction is selected by ICR2)
input
(edge direction is selected by ICR2)