HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 130

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Interrupt Controller (INTC)
6.3.3
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
cleared by writing 0 to IRQnF after reading IRQnF = 1.
Rev.4.00 Mar. 27, 2008 Page 84 of 882
REJ09B0108-0400
Bit
1
0
Bit
15 to 8 —
7
6
5
4
3
2
1
0
Bit Name
IRQ7ES1
IRQ7ES0
Bit Name Initial Value
IRQ0F
IRQ1F
IRQ2F
IRQ3F
IRQ4F
IRQ5F
IRQ6F
IRQ7F
IRQ Status Register (ISR)
All 0
Initial Value
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This bit sets the IRQ7 interrupt request edge
detection mode.
00: Interrupt request is detected on falling edge of
01: Interrupt request is detected on rising edge of
10: Interrupt request is detected on both of falling
11: Cannot be set
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
IRQ0 to IRQ7 Flags
These bits display the IRQ0 to IRQ7 interrupt request
status.
[Setting condition]
•
[Clearing conditions]
•
•
•
•
When interrupt source that is selected by ICR 1
and ICR2 has occurred.
When 0 is written after reading IRQnF = 1
When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and
rising edge.
When the DISEL bit of DTMR of DTC is 0, after
DTC has been started by IRQn interrupt.
IRQ7 input
IRQ7 input
and rising edge of IRQ7 input