HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 453

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Some bit functions of SSR differ between normal serial communication interface mode and smart
card interface mode.
• Normal serial communication interface mode (when SMIF in SDCR is 0)
Bit
7
Bit Name
TDRE
Serial Status Register (SSR)
Initial Value
1
R/W
R/(W)* Transmit Data Register Empty
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
•
Power-on reset or software standby mode
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
data can be written to TDR
When 0 is written to TDRE after reading TDRE =
1
When the DMAC is activated by a TXI interrupt
request.
When the DTC is activated by a TXI interrupt
request and transferred data to TDR while the
DISEL bit in DTMR of DTC is 0.
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 407 of 882
REJ09B0108-0400