HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 329

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 11.30 shows an example
of procedure for selecting the reset synchronized PWM mode.
Reset-synchronized PWM mode
Figure 11.30
PWM cycle output enabling,
PWM output level setting
Select counter clock and
Enable waveform output
Set reset-synchronized
Start count operation
Brushless DC motor
counter clear source
Reset-synchronized
Stop counting
control setting
PWM mode
PFC setting
PWM mode
Set TCNT
Set TGR
Procedure for Selecting Reset-Synchronized PWM Mode
Note: The output waveform starts to toggle operation at the point of
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
[1] Clear the CST3 and CST4 bits in the TSTR
[2] Set bits TPSC2-TPSC0 and CKEG1 and
[3] When performing brushless DC motor control,
[4] Reset TCNT_3 and TCNT_4 to H'0000.
[5] TGRA_3 is the period register. Set the waveform
[6] Select enabling/disabling of toggle output
[7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select
[8] Set the enabling/disabling of the PWM waveform output
[9] Set the port control register and the port I/O register.
[10] Set the CST3 bit in the TSTR to 1 to start the count
to 0 to halt the counting of TCNT. The
reset-synchronized PWM mode must be set
up while TCNT_3 and TCNT_4 are halted.
CKEG0 in the TCR_3 to select the counter
clock and clock edge for channel 3. Set bits
CCLR2-CCLR0 in the TCR_3 to select TGRA
compare-match as a counter clear source.
set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source
and output chopping or gate signal direct output.
period value in TGRA_3. Set the transition timing
of the PWM output waveforms in TGRB_3,
TGRA_4, and TGRB_4. Set times within the
compare-match range of TCNT_3.
synchronized with the PMW cycle using bit PSYE
in the timer output control register (TOCR), and set
the PWM output level with bits OLSP and OLSN.
the reset-synchronized PWM mode. Do not set to TMDR_4.
pin in TOER.
operation.
X ≤ TGRA_3 (X: set value).
11.
Rev.4.00 Mar. 27, 2008 Page 283 of 882
Multi-Function Timer Pulse Unit (MTU)
REJ09B0108-0400