HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 37

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 23.5 Example of Read Operation (Byte Read) ................................................................714
Figure 23.6 Example of Write Operation (Longword Write) .....................................................714
Figure 23.7 Example of Error Occurrence (Longword Read).....................................................714
Section 24 Power-Down Modes
Figure 24.1 NMI Timing in Software Standby Mode (Application Example) ...........................730
Section 26 Electrical Characteristics
Figure 26.1 Output Load Circuit.................................................................................................771
Figure 26.2 System Clock Timing ..............................................................................................773
Figure 26.3 EXTAL Clock Input Timing ...................................................................................773
Figure 26.4 Oscillation Settling Time.........................................................................................773
Figure 26.5 Reset Input Timing ..................................................................................................775
Figure 26.6 Interrupt Signal Input Timing..................................................................................775
Figure 26.7 Interrupt Signal Output Timing ...............................................................................776
Figure 26.8 Bus Release Timing.................................................................................................776
Figure 26.9 Basic Cycle (No Waits) ........................................................................................... 778
Figure 26.10 Basic Cycle (One Software Wait)..........................................................................779
Figure 26.11 Basic Cycle (Two Software Waits + Waits by WAIT Signal) ..............................780
Figure 26.12 DREQ0, DREQ1 Input Timing (1)........................................................................781
Figure 26.13 DREQ0, DREQ1 Input Timing (2)........................................................................782
Figure 26.14 DRAK Output Delay Time....................................................................................782
Figure 26.15 MTU Input/Output timing .....................................................................................783
Figure 26.16 MTU Clock Input Timing.......................................................................................783
Figure 26.17 I/O Port Input/Output timing .................................................................................784
Figure 26.18 WDT Timing .........................................................................................................785
Figure 26.19 SCI Input Timing...................................................................................................787
Figure 26.20 SCI Input/Output Timing.......................................................................................787
2
Figure 26.21 I
C Bus Interface Timing .......................................................................................789
Figure 26.22 POE Input/Output Timing .....................................................................................789
Figure 26.23 External Trigger Input Timing ..............................................................................790
Figure 26.24 H-UDI Clock Timing ............................................................................................791
Figure 26.25 H-UDI TRST Timing ............................................................................................792
Figure 26.26 H-UDI Input/Output Timing .................................................................................792
Figure 26.27 AUD Reset Timing................................................................................................794
Figure 26.28 Branch Trace Timing.............................................................................................794
Figure 26.29 RAM Monitor Timing ...........................................................................................794
Appendix D I/O Port Block Diagrams
Figure D.1 PAn/RXDm ..............................................................................................................813
Figure D.2 PAn/TXDm...............................................................................................................814
Figure D.3 PAn/SCKm/DREQm/IRQm .....................................................................................815
Rev.4.00 Mar. 27, 2008, Page xxxv of xliv
REJ09B0108-0400