HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 780

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25. List of Registers
25.1
Access sizes are indicated with the number of bits. Access states are indicated with the number of
specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or
32-bit access (L).
Note: Access to undefined or reserved addresses is prohibited. Correct operation cannot be
Rev.4.00 Mar. 27, 2008 Page 734 of 882
REJ09B0108-0400
Register name
⎯
Serial mode register_0
Bit rate register_0
Serial control register_0
Transmit data register_0
Serial status register_0
Receive data register_0
Serial direction control register_0
⎯
Serial mode register_1
Bit rate register_1
Serial control register_1
Transmit data register_1
Serial status register_1
Receive data register_1
Serial direction control register_1
⎯
Serial mode register_2
Bit rate register_2
Serial control register_2
Transmit data register_2
Serial status register_2
Receive data register_2
Serial direction control register_2
guaranteed if these addresses are accessed.
Register Address Table (In the Order from Lower Addresses)
abbreviation
⎯
SMR_0
BRR_0
SCR_0
TDR_0
SSR_0
RDR_0
SDCR_0
⎯
SMR_1
BRR_1
SCR_1
TDR_1
SSR_1
RDR_1
SDCR_1
⎯
SMR_2
BRR_2
SCR_2
TDR_2
SSR_2
RDR_2
SDCR_2
NO. of bits Address
⎯
8
8
8
8
8
8
8
⎯
8
8
8
8
8
8
8
⎯
8
8
8
8
8
8
8
H'FFFF8000 to
H'FFFF819F
H'FFFF81A0
H'FFFF81A1
H'FFFF81A2
H'FFFF81A3
H'FFFF81A4
H'FFFF81A5
H'FFFF81A6
H'FFFF81A7 to
H'FFFF81AF
H'FFFF81B0
H'FFFF81B1
H'FFFF81B2
H'FFFF81B3
H'FFFF81B4
H'FFFF81B5
H'FFFF81B6
H'FFFF81B7 to
H'FFFF81BF
H'FFFF81C0
H'FFFF81C1
H'FFFF81C2
H'FFFF81C3
H'FFFF81C4
H'FFFF81C5
H'FFFF81C6
Module
⎯
SCI
(Channel 0)
⎯
SCI
(Channel 1)
⎯
SCI
(Channel 2)
Access size
⎯
8, 16
8
8, 16
8
8, 16
8
8
⎯
8, 16
8
8, 16
8
8, 16
8
8
⎯
8, 16
8
8, 16
8
8, 16
8
8
NO. of Access states
⎯
Pφ reference
B:2
W:4