HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 79

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Classification Types
Arithmetic
operations
Logic
operations
Shift
Branch
6
10
9
Operation
Code
SUBC
SUBV
AND
NOT
OR
TAS
TST
XOR
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
Function
Binary subtraction with borrow
Binary subtraction with underflow
Logical AND
Bit inversion
Logical OR
Memory test and bit set
Logical AND and T bit set
Exclusive OR
One-bit left rotation
One-bit right rotation
One-bit left rotation with T bit
One-bit right rotation with T bit
One-bit arithmetic left shift
One-bit arithmetic right shift
One-bit logical left shift
n-bit logical left shift
One-bit logical right shift
n-bit logical right shift
Conditional branch, conditional branch with
delay (Branch when T = 0)
Conditional branch, conditional branch with
delay (Branch when T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
Rev.4.00 Mar. 27, 2008 Page 33 of 882
REJ09B0108-0400
No. of
Instructions
33
14
14
11
2. CPU