HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 34

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 452
Figure 13.23 Direct Convention (DIR = SINV = O/E = 0)......................................................... 452
Figure 13.24 Inverse Convention (DIR = SINV = O/E = 1)....................................................... 453
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
Figure 13.26 Retransfer Operation in SCI Transmit Mode......................................................... 457
Figure 13.27 TEND Flag Generation Timing in Transmit Operation......................................... 457
Figure 13.28 Example of Transmit Processing Flow.................................................................. 458
Figure 13.29 Timing for Fixing Clock Output Level.................................................................. 459
Figure 13.30 Example of Clocked Synchronous Transmission with DMAC/DTC .................... 464
Section 14 I
Figure 14.1 A Block Diagram of the I
Figure 14.2 Example of the Connection of I
Figure 14.3 I
Figure 14.4 I
Figure 14.5 I
Figure 14.6 An Example of IIC Initialization Flowchart............................................................ 495
Figure 14.7 Example: Flowchart of Operations in the Master Transmit Mode .......................... 497
Figure 14.8 An Example of the Timing of Operations in Master Transmit Mode
Figure 14.9 An Example of the Stop Condition Issuance Timing in Master Transmit Mode
Figure 14.10 Example: Flowchart of Operations in the Master Receive Mode (HNDS = 1) ..... 502
Figure 14.11 An Example of the Timing of Operations in Master Receive Mode
Figure 14.12 An Example of the Stop Condition Issuance Timing in Master Receive Mode
Figure 14.13 Example: Flowchart of Operations in Master Receive Mode
Figure 14.14 Example: Flowchart of Operations in Master Receive Mode
Figure 14.15 An Example of the Timing of Operations in Master Receive Mode
Figure 14.16 An Example of the Stop Condition Issuance Timing in Master Receive Mode
Figure 14.17 Example: Flowchart of Operations in the Slave Receive Mode (HNDS = 1) ....... 510
Figure 14.18 An Example of the Timing of Operations in Slave Receive Mode 1
Rev.4.00 Mar. 27, 2008 Page xxxii of xliv
REJ09B0108-0400
(MLS = WAIT = 0) ................................................................................................. 499
(MLS = WAIT = 0) ................................................................................................. 500
(This LSI Is the Master Device).............................................................................. 470
2
2
2
2
C Bus Interface (IIC) Option
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 504
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 504
(Multiple Bytes Reception) (WAIT = 1) ............................................................... 505
(One Byte Reception) (WAIT = 1)........................................................................ 506
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 508
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 509
(MLS = 0, HNDS = 1)........................................................................................... 512
(Using Clock of 372 Times Bit Rate).................................................................... 454
C Bus Data Format (I
C Bus Data Format (Serial Format) ...................................................................... 493
C Bus Timing ........................................................................................................ 494
2
C Bus Format) ................................................................... 493
2
C Bus Interface .............................................................. 469
2
C Bus Interfaces