HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 536

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
14.3.7
SCRX enables or disables I
transmission.
Rev.4.00 Mar. 27, 2008 Page 490 of 882
REJ09B0108-0400
Bit
7, 6
5
4
3
2
2
C Bus Interface (IIC) Option
Bit Name
⎯
IICX
IICE
HNDS
⎯
Serial Control Register X (SCRX)
Initial Value
All 0
0
0
0
0
2
C bus interface interrupts and confirms the state of reception and
R
R/W
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
I
Along with bits CKS2 to CKS0 in the I
register (ICMR), this bit selects the transfer rate in the
master mode. For details on setting the transfer rate,
see table 14.3.
I
This bit controls access by the CPU to the I
interface registers (ICCR, ICSR, ICDR/SARX, and
ICMR/SAR) of the I
0: Disables CPU access to the registers of the I
1: Enables CPU access to the registers of the I
Hand-Shake Receive Select
This bit enables/disables continuous reception in
receive mode.
When the HNDS bit is cleared to 0, receive operation
is performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level thus disabling the next data to be transferred.
The bus line is released and next frame receive
operation is enabled by reading the receive data in
ICDR.
Reserved
This bit is always read as 0. The write value should
always be 0.
2
2
C Transfer Rate Select
C master Enable
interface.
interface.
2
C bus interface.
2
C bus mode
2
C bus
2
2
C bus
C bus