HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 31

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 11.57 Output Compare Output Timing (Normal Mode/PWM Mode).............................314
Figure 11.58 Output Compare Output Timing (Complementary PWM Mode/
Figure 11.59 Input Capture Input Signal Timing........................................................................315
Figure 11.60 Counter Clear Timing (Compare Match)...............................................................316
Figure 11.61 Counter Clear Timing (Input Capture) ..................................................................316
Figure 11.62 Buffer Operation Timing (Compare Match)..........................................................317
Figure 11.63 Buffer Operation Timing (Input Capture) .............................................................317
Figure 11.64 TGI Interrupt Timing (Compare Match) ...............................................................318
Figure 11.65 TGI Interrupt Timing (Input Capture) ...................................................................318
Figure 11.66 TCIV Interrupt Setting Timing..............................................................................319
Figure 11.67 TCIU Interrupt Setting Timing..............................................................................319
Figure 11.68 Timing for Status Flag Clearing by CPU...............................................................320
Figure 11.69 Timing for Status Flag Clearing by DTC/DMAC Activation................................320
Figure 11.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................321
Figure 11.71 Contention between TCNT Write and Clear Operations .......................................322
Figure 11.72 Contention between TCNT Write and Increment Operations ...............................323
Figure 11.73 Contention between TGR Write and Compare Match...........................................324
Figure 11.74 Contention between Buffer Register Write and Compare Match (Channel 0) ......325
Figure 11.75 Contention between Buffer Register Write and Compare Match
Figure 11.76 Contention between TGR Read and Input Capture ...............................................326
Figure 11.77 Contention between TGR Write and Input Capture ..............................................327
Figure 11.78 Contention between Buffer Register Write and Input Capture..............................328
Figure 11.79 TCNT_2 Write and Overflow/Underflow Contention with Cascade
Figure 11.80 Counter Value during Complementary PWM Mode Stop.....................................330
Figure 11.81 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM
Figure 11.82 Reset Synchronous PWM Mode Overflow Flag ...................................................332
Figure 11.83 Contention between Overflow and Counter Clearing............................................333
Figure 11.84 Contention between TCNT Write and Overflow...................................................334
Figure 11.85 Error Occurrence in Normal Mode, Recovery in Normal Mode ...........................339
Figure 11.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1...........................340
Figure 11.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2...........................341
Figure 11.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ..............342
Figure 11.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM
Figure 11.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM
Reset Synchronous PWM Mode) ..........................................................................315
(Channels 3 and 4).................................................................................................326
Connection.............................................................................................................329
Mode......................................................................................................................331
Mode......................................................................................................................343
Mode......................................................................................................................344
Rev.4.00 Mar. 27, 2008, Page xxix of xliv
REJ09B0108-0400