HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 541

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.4.2
Initialize the IIC following the procedure shown below before starting the data transmission or
reception.
Clear the IRIC flag in ICCR
Initialization
Figure 14.6 An Example of IIC Initialization Flowchart
<<Transmission/reception start>>
No
Read the IRIC flag in ICCR
Set MSTP21 = 0 (MSTCR1)
Set IICE = 1 (SCRX)
Set PBCR1, PBCR2
Set ICE = 0 (ICCR)
Set ICE = 1 (ICCR)
Initialization start
Set SAR, SARX
Set SCRX
Set SCRX
Set ICMR
Set ICCR
Set ICSR
IRIC = 0?
Yes
Cancel module stop mode
Enable the CPU access to the IIC control registerand data
register.
Enable SAR and SARX to be accessed
Set the first slave address, second slave address,and IIC
transfer format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an I
Set acknowledge bit
(ACKB)
Set transfer rate
(IICX)
(MLS, WAIT, and CKS2 to CKS0)
Enable interrupt
(STOPIM and HNDS)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Set transfer format, wait insertion, and transfer rate
Rev.4.00 Mar. 27, 2008 Page 495 of 882
14. I
2
C port
2
C Bus Interface (IIC) Option
REJ09B0108-0400