HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 181

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.4.3
The following is a DTC use example of a 128-byte data reception by the SCI:
1. The settings are: DTMR source address fixed (SM1 = SM0 = 0), destination address
2. Set the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
6. When DTCRA is 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
incremented (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), byte size (SZ1 = SZ0 =
0), one transfer per activating source (CHNE = 0), and a CPU interrupt request after the
designated number of data transfers (DISEL = 0). DTS bit can be set to any value. 128
(H'0080) is set in DTCRA, the RDR address of the SCI is set in DTSAR, and the start address
of the RAM storing the receive data is set in DTDAR. DTCRB can be set to any value.
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DTDAR is incremented and DTCRA is decremented. The RDRF flag is
automatically cleared to 0.
corresponding bit in DTER is cleared to 0, and an RXI interrupt request is sent to the CPU.
The interrupt handling routine should perform completion processing.
DTC Use Example
Rev.4.00 Mar. 27, 2008 Page 135 of 882
8. Data Transfer Controller (DTC)
REJ09B0108-0400