HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 530

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
Table 14.5 The Relationship between Flags and Transfer States (Slave Mode)
Rev.4.00 Mar. 27, 2008 Page 484 of 882
REJ09B0108-0400
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
1↑/0
(*
0
1↑/0
(*
1
1
1
1
1
1
0
0
0
0
0
⎯
C Bus Interface (IIC) Option
1
1
)
)
0
1↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑/0
(*
3
)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1↑
(*
3
)
0
0
0
0
1↑
⎯
1↑/0
(*
⎯
⎯
⎯
1↑/0
(*
1↑/0
(*
⎯
⎯
⎯
1↑/0
(*
⎯
2
2
2
2
)
)
)
)
0
0↓
0
0
1↑
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0
⎯
⎯
⎯
⎯
⎯
0↓ 0↓
⎯
0↓ 0↓
0
⎯
0↓ 0↓
⎯
0↓ 0↓
0
⎯
0
0
1↑
1↑
0
⎯
⎯
⎯
0
⎯
⎯
0
⎯
0
0
0
1↑
0
0
0
0
0
0
0
⎯
0↓
⎯
0↓
0
⎯
0
0
0
0
0
1↑
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1↑
1↑
1↑
⎯
⎯
⎯
⎯
⎯
⎯
1↑
0↓
1
0↓
1↑
⎯
ICDRE State
0
1↑
1
1
1
⎯
1↑
0↓
1
0↓
1↑
⎯
⎯
⎯
⎯
⎯
0↓
Idle state (flag clearing
required)
Start condition detected
SAR match in the first frame
(SARX ≠ SAR)
General call address match
in the first frame (SARX ≠
H'00)
SARX match in the first
frame (SAR ≠ SARX)
Transmission end
(ACKE = 1 and ACKB = 1)
Transmission end with
ICDRE = 0
ICDR write with the above
state
Transmission end with
ICDRE = 1
ICDR write with the above
state
Automatic data transfer from
ICDRT to ICDRS in the
above state
Reception end with
ICDRF = 0
ICDR read with the above
state
Reception end with
ICDRF = 1
ICDR read with the above
state
Automatic data transfer from
ICDRS to ICDRR with the
above state
Stop condition detected