HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 461

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.3.8
SDCR selects LSB-first or MSB-first transfer and sets the smart card interface. With an 8-bit data
length, LSB-first/MSB-first selection is available regardless of the communication mode. With a
7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-
first transfer.
Bit
7 to
4
3
2
1
0
Bit Name
⎯
DIR
SINV
⎯
SMIF
Serial Direction Control Register (SDCR)
Initial Value
All 1
0
0
1
0
R/W
R
R/W
R/W
R
R/W
Description
Reserved
The write value should always be 1. Operation
cannot be guaranteed if 0 is written.
Data Transfer Direction
Selects the serial/parallel conversion direction.
0: Transfer in LSB-first
1: Transfer in MSB-first
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
Smart Card Data Invert
Specifies inversion of the data logic level. The SINV
bit does not affect the logic level of the parity bit. To
invert the parity bit, invert the O/E bit in SMR.
This bit is valid only in smart card interface mode. In
normal asynchronous mode or clocked synchronous
mode, clear this bit to 0.
0: TDR contents are transmitted as they are. Receive
1: TDR contents are inverted before being
Reserved
This bit is always read as 1 and cannot be modified.
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in smart
card interface mode.
0: Normal asynchronous mode or clocked
1: Smart card interface mode
data is stored as it is in RDR
transmitted. Receive data is stored in inverted form
in RDR
synchronous mode
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 415 of 882
REJ09B0108-0400