HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 506

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
13.8
13.8.1
Table 13.12 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the
DMAC or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data
transfer is performed by the DMAC or DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DMAC or DTC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Rev.4.00 Mar. 27, 2008 Page 460 of 882
REJ09B0108-0400
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode