HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 41

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Section 3 MCU Operating Modes
Table 3.1
Table 3.2
Table 3.3
Section 4 Clock Pulse Generator
Table 4.1
Table 4.2
Table 4.3
Section 5 Exception Processing
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Table 5.10
Table 5.11
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Initial Values of Registers.......................................................................................18
Sign Extension of Word Data .................................................................................21
Delayed Branch Instructions...................................................................................22
T Bit ........................................................................................................................22
Immediate Data Accessing......................................................................................23
Absolute Address Accessing...................................................................................23
Displacement Accessing .........................................................................................24
Addressing Modes and Effective Addresses...........................................................25
Instruction Formats .................................................................................................29
Classification of Instructions ..................................................................................32
Selection of Operating Modes.................................................................................47
Clock Mode Setting ................................................................................................48
Pin Configuration....................................................................................................49
Operating Clock for Each Module ..........................................................................54
Damping Resistance Values (Recommended Values) ............................................55
Crystal Resonator Characteristics ...........................................................................56
Types of Exception Processing and Priority Order .................................................61
Timing for Exception Source Detection and Start of Exception Processing...........62
Exception Processing Vector Table ........................................................................63
Calculating Exception Processing Vector Table Addresses....................................64
Reset Status.............................................................................................................65
Bus Cycles and Address Errors...............................................................................67
Interrupt Sources.....................................................................................................69
Interrupt Priority .....................................................................................................70
Types of Exceptions Triggered by Instructions ......................................................71
Generation of Exception Sources Immediately after Delayed Branch
Stack Status after Exception Processing Ends ........................................................74
Pin Configuration....................................................................................................79
Interrupt Exception Processing Vectors and Priorities............................................90
Interrupt Response Time.........................................................................................96
Instruction or Interrupt-Disabled Instruction ..........................................................73
Tables
Rev.4.00 Mar. 27, 2008, Page xxxix of xliv
REJ09B0108-0400