HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 18

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Watchdog Timer (WDT) .................................................................379
12.1 Features............................................................................................................................. 379
12.2 Input/Output Pin................................................................................................................ 380
12.3 Register Descriptions ........................................................................................................ 381
12.4 Operation .......................................................................................................................... 385
12.5 Interrupt Source ................................................................................................................ 388
12.6 Usage Notes ...................................................................................................................... 389
Section 13 Serial Communication Interface (SCI) ............................................393
13.1 Features............................................................................................................................. 393
13.2 Input/Output Pins .............................................................................................................. 395
13.3 Register Descriptions ........................................................................................................ 396
Rev.4.00 Mar. 27, 2008 Page xvi of xliv
REJ09B0108-0400
11.9.4 Operation ............................................................................................................. 375
11.9.5 Usage Notes ......................................................................................................... 377
12.3.1 Timer Counter (TCNT)........................................................................................ 381
12.3.2 Timer Control/Status Register (TCSR)................................................................ 382
12.3.3 Reset Control/Status Register (RSTCSR)............................................................ 384
12.4.1 Watchdog Timer Mode ........................................................................................ 385
12.4.2 Interval Timer Mode ............................................................................................ 386
12.4.3 Clearing Software Standby Mode ........................................................................ 387
12.4.4 Timing of Setting Overflow Flag (OVF) ............................................................. 387
12.4.5 Timing of Setting Watchdog Timer Overflow Flag (WOVF) ............................. 388
12.6.1 Notes on Register Access..................................................................................... 389
12.6.2 TCNT Write and Increment Contention .............................................................. 390
12.6.3 Changing CKS2 to CKS0 Bit Values .................................................................. 391
12.6.4 Changing between Watchdog Timer and Interval Timer Modes ......................... 391
12.6.5 System Reset by WDTOVF Signal...................................................................... 391
12.6.6 Internal Reset in Watchdog Timer Mode............................................................. 391
12.6.7 Manual Reset in Watchdog Timer Mode ............................................................. 392
12.6.8 Note on Using WDTOVF Signal ......................................................................... 392
13.3.1 Receive Shift Register (RSR) .............................................................................. 398
13.3.2 Receive Data Register (RDR) .............................................................................. 398
13.3.3 Transmit Shift Register (TSR) ............................................................................. 398
13.3.4 Transmit Data Register (TDR)............................................................................. 398
13.3.5 Serial Mode Register (SMR) ............................................................................... 399
13.3.6 Serial Control Register (SCR).............................................................................. 402
13.3.7 Serial Status Register (SSR) ................................................................................ 407
13.3.8 Serial Direction Control Register (SDCR)........................................................... 415
13.3.9 Bit Rate Register (BRR) ...................................................................................... 416