HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 13

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Interrupt Controller (INTC) .............................................................. 77
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Section 7 User Break Controller (UBC) ........................................................... 101
7.1
7.2
7.3
7.4
Features .............................................................................................................................77
Input/Output Pins ..............................................................................................................79
Register Descriptions ........................................................................................................79
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources ...............................................................................................................87
6.4.1
6.4.2
6.4.3
6.4.4
Interrupt Exception Processing Vectors Table ..................................................................90
Operation...........................................................................................................................93
6.6.1
6.6.2
Interrupt Response Time ...................................................................................................96
Data Transfer with Interrupt Request Signals ...................................................................98
6.8.1
6.8.2
6.8.3
6.8.4
Features .............................................................................................................................101
Register Descriptions ........................................................................................................103
7.2.1
7.2.2
7.2.3
7.2.4
Operation...........................................................................................................................106
7.3.1
7.3.2
7.3.3
Examples of Use ...............................................................................................................109
Interrupt Control Register 1 (ICR1).....................................................................80
Interrupt Control Register 2 (ICR2).....................................................................82
IRQ Status Register (ISR)....................................................................................84
Interrupt Priority Registers A to J (IPRA to IPRJ)...............................................85
External Interrupts ...............................................................................................87
On-Chip Peripheral Module Interrupts ................................................................88
User Break Interrupt ............................................................................................88
H-UDI Interrupt ...................................................................................................89
Interrupt Sequence ...............................................................................................93
Stack after Interrupt Exception Processing ..........................................................95
Handling Interrupt Request Signals as Sources for DTC Activating and
CPU Interrupt, but Not DMAC Activating ..........................................................99
Handling Interrupt Request Signals as Sources for Activating DMAC,
but Not CPU Interrupt and DTC Activating ........................................................99
Handling Interrupt Request Signals as Source for DTC Activating,
but Not CPU Interrupt and DMAC Activating ....................................................99
Handling Interrupt Request Signals as Source for CPU Interrupt
but Not DMAC and DTC Activating ...................................................................100
User Break Address Register (UBAR) ................................................................103
User Break Address Mask Register (UBAMR) ...................................................103
User Break Bus Cycle Register (UBBR) .............................................................104
User Break Control Register (UBCR)..................................................................105
Flow of User Break Operation .............................................................................106
Break on On-Chip Memory Instruction Fetch Cycle ...........................................108
Program Counter (PC) Values Saved...................................................................108
Rev.4.00 Mar. 27, 2008, Page xi of xliv
REJ09B0108-0400