HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 581

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9. Points for caution in the execution of the instruction that sets the I
10. Notes on WAIT function
condition
If the rise time in the 9th cycle of SCL exceeds the specified value due to a high bus-load
capacitance, or if a slave device inserts a wait by setting the level on SCL low, read SCL after
the rise of 9th cycle of the clock to confirm that the level is low, and then execute the
instruction that sets the stop condition.
⎯ Conditions to cause this phenomenon
⎯ Error phenomenon
⎯ Restrictions
SCL
SDA
IRIC
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
and the fall of the 8th clock.
Figure 14.31 Timing for the Setting of the Stop Condition
VIH
9
th
cycle
since this waveform takes
SCL is detected as low
a long time to rise.
Period for securing
the high-level period
[1] Decision on whether
or not SCL is low
Rev.4.00 Mar. 27, 2008 Page 535 of 882
[2] Stop condition instruction
generation
14. I
2
C bus interface stop
2
C Bus Interface (IIC) Option
Stop condition
REJ09B0108-0400