HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 196

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9. Bus State Controller (BSC)
Rev.4.00 Mar. 27, 2008 Page 150 of 882
REJ09B0108-0400
Bit
5
4
3
Bit Name Initial Value R/W
CW1
CW0
SW3
1
1
1
R/W
R/W
R/W
Description
Idle cycles at continuous access to CS1 and CS5 spaces
This bit inserts an idle cycle and negates the CS1 signal to
make the bus cycle end obvious when accessing the CS1
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS5 space after
access to the CS1 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS5 space, and when access is made to the CS1 space
after access to the CS5 space.
0: No idle cycle inserted at continuous access to the CS1
1: One idle cycle inserted at continuous access to the CS1
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
Idle cycles at continuous access to CS0 and CS4 spaces
This bit inserts an idle cycle and negates the CS0 signal to
make the bus cycle end obvious when accessing the CS0
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS4 space after
access to the CS0 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS4 space, and when access is made to the CS0 space
after access to the CS4 space.
0: No idle cycle inserted at continuous access to the CS0
1: One idle cycle inserted at continuous access to the CS0
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
CS assert period extension for CS3 and CS7 spaces
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS3 and
CS7.
0: No cycle inserted for CS assert period for CS3 and CS7
1: CS assert extension for CS3 and CS7 spaces.
spaces.
and CS5 spaces.
and CS5 spaces.
and CS4 spaces.
and CS4 spaces.
(Each one cycle inserted before and after the bus cycle)