HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 456

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
Note:
Rev.4.00 Mar. 27, 2008 Page 410 of 882
REJ09B0108-0400
Bit
2
1
0
Bit Name
TEND
MPB
MPBT
*
Only 0 can be written to clear the flag.
1
0
0
Initial Value
R/W
R
R
R/W
Description
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
•
Multiprocessor Bit
Stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0, its previous
state is retained.
Multiprocessor Bit Transfer
Sets the multiprocessor bit value to be added to the
transmit data.
Power-on reset or software standby mode
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
When 0 is written to TDRE after reading TDRE =
1
When the DMAC is activated by a TXI interrupt
request.
When the DTC is activated by a TXI interrupt and
transmit data is written to TDR while the DISEL
bit in DTMR of DTC is 0.