HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 164

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Data Transfer Controller (DTC)
8.2.2
The DTC source address register (DTSAR) is a 32-bit register that specifies the DTC transfer
source address. For the word size transfer, specify an even source address. For the longword size
transfer, specify a multiple-of-four address.
The initial value of DTSAR is undefined.
8.2.3
The DTC destination address register (DTDAR) is a 32-bit register that specifies the DTC transfer
destination address. For the word size transfer, specify an even source address. For the longword
size transfer, specify a multiple-of-four address.
The initial value of DTDAR is undefined.
8.2.4
The DTC initial address register (DTIAR) is a 32-bit register that specifies the initial transfer
source/transfer destination address in repeat mode. In repeat mode, when the DTS bit is set to 1,
specify the initial transfer source address in the repeat area, and when the DTS bit is cleared to 0,
specify the initial transfer destination address in the repeat area.
The initial value of DTIAR is undefined.
8.2.5
DTCRA is a 16-bit register that designates the number of times data is to be transferred by the
DTC.
In normal mode, the DTCRA functions as a 16-bit transfer counter (1 to 65536). It is decremented
by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The number
of transfers is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is
H'0000.
In repeat mode, upper 8-bit DTCRAH maintains the transfer count value and lower 8-bit
DTCRAL functions as an 8-bit transfer counter. The number of transfers is 1 when the set value is
DTCRAH = DTCRAL = H'01, 255 when they are H'FF, and 256 when it is H'00.
In block transfer mode, the DTCRA functions as a 16-bit transfer counter. The number of transfers
is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000.
Rev.4.00 Mar. 27, 2008 Page 118 of 882
REJ09B0108-0400
DTC Source Address Register (DTSAR)
DTC Destination Address Register (DTDAR)
DTC Initial Address Register (DTIAR)
DTC Transfer Count Register A (DTCRA)